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IEEE INTERNATIONAL WORKSHOP on DEFECT & ADAPTIVE TEST ANALYSIS
(DATA 2012)

November 8-9, 2012
Disneyland Hotel, Anaheim, CA, USA

http://DATA.tttc-events.org/

held in conjunction with ITC / Test Week 2012

CALL FOR PAPERS
Scope -- Submissions -- Key Dates -- Additional Information -- Committees
Scope

It just never stops. Every year silicon wafer process technology continues to shrink, more transistors and functions are included into designs, and customers continue to demand even lower dppm. Meanwhile our bosses and managers are always looking at test as an area to reduce product cost, and they expect us to be able to reduce our test costs while also meeting these newer and tougher test challenges and quality goals. So how do we do it?

“How to get more out of test” has led to new methods to learn about defects and IC behavior through the use of innovative analysis techniques. Now questions about how these techniques should be executed and controlled in production, the types and sizes of databases, and even the format and storage of test data itself are becoming critical. Complex problems, such as the control and documentation of dynamic test changes during Adaptive Test, ensuring high quality levels without test escapes, and the practical and realistic limitations of new ideas for board/system testing are all hot industry topics. Closing the knowledge gap about these issues, the processes, the new test techniques, new database requirements, and how defect models and failure data can be used to adapt test flows are the goals of the DATA workshop.

Presentations related to the topics listed below, including papers, case studies, and posters, are being requested for the 2012 workshop on Defect and Adaptive Test Analysis:

Outlier Identification
Test Data Analysis
Data-Mining Methods for Test Data Processing
Data-Driven Testing (DDT)
Yield Learning and Analysis
Adaptive Test Database requirements
High/Low Voltage Testing & Stress Testing
Transition and Delay Fault Testing

Reliability and Yield
Nanometer Test Challenges
Defect Coverage & Metrics
Mixed Current/Voltage Testing
Economics of Defect Based Testing
Fault Localization & Diagnosis
Noise and Crosstalk Testing
In-System or On-board Testing

Submissions

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To present at the workshop, send to Arani.Sinha@INTEL.com a PDF version of an extended abstract of at least 1000 words or a full paper (Max 10 pages, double column, 11pt font size, IEEE proceeding format) by August 15, 2012. Each submission should include full name and address of each author, affiliation, telephone number, FAX and Email address. Camera-ready papers for inclusion in the digest of papers will be due on Oct 15, 2012. Presentations on cutting edge test technology, innovative test ideas, and industrial practices and experience are welcome. Ideas or proposals for Embedded Tutorials, Debates, Panel Discussions or “Spot-Light” presentations describing industrial experiences are also invited.
Key Dates

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Submission deadline: August 15, 2012
Notification of acceptance: September 7, 2012
Camera ready paper: October 15, 2012

Final copy deadline: November 2, 2012

Additional Information
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Technical Program Submissions:
Arani Sinha
Intel, USA.
E-mail: Arani.Sinha@INTEL.com

General Information:
Jeffrey Roehr
Texas Instruments, USA.
E-mail: JLRoehr@TI.com

Committees
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GENERAL CHAIR
Jeffrey Roehr, Texas Instruments

PROGRAM CHAIR
Arani Sinha, Intel

VICE-PROGRAM CHAIR
Jennifer Dworak, SMU

PANEL CHAIR
Wesley Smith, Galaxy

FINANCE CHAIR
Sankaran Menon, Intel

PUBLICITY CHAIR
Kanad Chakraborty, Lattice Semi

PUBLICATIONS CHAIR
Chintan Patel, UMBC

STEERING COMMITTEE
Sankaran Menon, Intel
Adit Singh, Auburn Univ.
M. Tehranipoor, U Connecticut
Hank Walker, Texas A&M
Hans Manhaeve, Q-Star Test
Jim Plusquellic, U. New Mexico

PROGRAM COMMITTEE
Rob Aitken, ARM
Nemat Bidokhti, Cisco
Sreejit Chakravarty, LSI
John Carulli, TI
Jennifer Dworak, SMU
Patrick Girard, LIRMM, France
Ajay Khoche, Consultant
Mike Laisne, Qualcomm
Amit Nahar, TI
Suriyaprakash Natarajan, Intel 
Jay Orbon, Consultant
John Potter, Asset-Intertech
Rajesh Raina, Freescale
Claude Thibeault, ETS, Canada
Li C. Wang, UCSB     
Xiaoqing Wen, KIT, Japan
Qiang Xu, CUHK, Hong Kong

For more information, visit us on the web at: http://DATA.tttc-events.org/

The IEEE INTERNATIONAL WORKSHOP on DEFECT & ADAPTIVE TEST ANALYSIS (DATA 2012) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

PAST CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

TTTC 1ST VICE CHAIR
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

SECRETARY
Joan FIGUERAS
UPC Barcelona Tech - Spain
Tel. +
E-mail figueras@eel.upc.edu

ITC GENERAL CHAIR
Doug YOUNG
BVC Industrial - USA
Tel. +1-602-617-0393
E-mail doug0037@aol.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Athens
- Greece
Tel. +30-210-7275145
E-mail dgizop@di.uoa.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Giorgio DI NATALE
LIRMM - France
Tel. +33-4-6741-8501
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 2ND VICE CHAIR
Rohit KAPUR
Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
Krish CHAKRABARTY
Duke University - USA
Tel. +1-
E-mail krish@ee.duke.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chen-huan.chiang@alcatel-lucent.com

TECHNICAL ACTIVITIES
Patrick GIRARD
LIRMM – France
Tel.+33 467 418 629
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
Tel. +81 743 72 5221
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com